The clock is ticking...

Over the past 2 days I've been working on the clock implementation. The book describes a simple clock based on connecting a NOT gate to itself. Then it goes on to explain that you can create a delayed signal by "attaching a length of wire to the clock". Not so easy to do in a virtual clock like I'm building...

So I ended up having to modify the clock design slightly.

In my program, along with a standard NOT gate, I also have a special dummy gate, which I call CONN, which is a simple passthrough. I needed this contruct in some occasions to connect 2 wires together. It is built simply like this by connecting 2 NOT gates:

So by creating the basic clock using a CONN and a NOT gate as such:

I can get the delayed signal on the clkd wire. I also have a way to "pause" certain wires for a specific amount of time to simulate the actual delay. Basically this clock operates in "quarter ticks", and allows to simulate the bevaviour in the book. Here is an output from the test suite @ 1Hz, with "clock debug" turned on:

You an see the qticks happening in the order described in the graph from the book.