ALU done!

I spent the weekend refactoring my code since I wasn't happy with the way I had implemented the "wires", "pins" and "gates", along with the interaction patterns between them.

Now everything is clean, and I have completed and tested the ALU. Here's the output of my test suite so far:

Getting Started!

So about a week ago I stumbled upon this fabulous book:

But How do it Know? by J. Clark Scott
http://www.buthowdoitknow.com/

It is a book that teaches very well the inner workings of a computer, down to the logical gate level. As I follow along the book slowly, I decided to try to implement the computer in the book in my favorite programming language, Perl!

I know it's going to be slow and ugly, but that's ok.

My code is here if you are curious: https://github.com/patrickleboutillier/jcscpu

I've started this blog a week into the project, so I already have quite a bit done:

• All the basic gates are implemented
• All the compoments required to build the RAM module are completed
• The RAM module is completed
• All the compoments required to build the ALU module are completed

I'm currently building the ALU.

Biggest challenges so far are:

Difficulty debugging

To aid here I have quite an exhaustive test suite of over 5000 unit tests, but debugging NAND gates and the like can be a real nightmare. Respect to the people who built these things early on using real gates and wires!

BUS issues

Setting wire values to 0s and 1s is not the same thing as electricity flowing on a circuit. I have run into a few issues related to I/O BUSes, namely that when they are use as input, they leave values on the wires that prevent subsequent output events from being triggered. So far I fixed this a bit clumsily, so we'll see how it goes from here. This may reveal not to be an issue once the clock control the event in a more precise order.